CHES 2005

Edinburgh, UK

Josyula R. Rao Berk Sunar (Eds.): Cryptographic Hardware and Embedded Systems – CHES 2005: 7th International Workshop, Edinburgh, UK, August 29 – September 1, 2005. Proceedings. Lecture Notes in Computer Science, Vol 3659, Springer, 2005, ISBN: 3-540-28474-5

Read the paper abstracts. More »

Side Channels I

• William Dupuy, S´ebastien Kunz-Jacques: Resistance of Randomized Projective Coordinates Against Power Analysis p. 1
• Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi, Kai Schramm: Templates as Master Keys p. 15
• Werner Schindler, Kerstin Lemke, Christof Paar: A Stochastic Model for Differential Side Channel Cryptanalysis p. 30

Arithmetic for Cryptanalysis

• Jean S´ebastien Coron, David Lefranc, Guillaume Poupard: A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis p. 47
• P.J. Green, R. Noad, N.P. Smart: Further Hidden Markov Model Cryptanalysis p. 61

Low Resources

• Johann Großsch¨adl, Roberto M. Avanzi, Erkay Sava¸s, Stefan Tillich: Energy-Efficient Software Implementation of Long Integer Modular Arithmetic p. 75
• Katsuyuki Okeya, Tsuyoshi Takagi, Camille Vuillaume: Short Memory Scalar Multiplication on Koblitz Curves p. 91
• Lejla Batina, David Hwang, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede: Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051 µP p. 106

Special Purpose Hardware

• Jens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl,Christine Priplata, Colin Stahlke: SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers p. 119
• Willi Geiselmann, Adi Shamir, Rainer Steinwandt, Eran Tromer: Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization p. 131
• Marco Bucci, Raimondo Luzzi: Design of Testable Random Bit Generators p. 147

Hardware Attacks and Countermeasures I

• Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald: Successfully Attacking Masked AES Hardware Implementations p. 157
• Thomas Popp, Stefan Mangard: Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints p 172
• Wieland Fischer, Berndt M. Gammel: Masking at Gate Level in the Presence of Glitches p. 187

Arithmetic for Cryptography

• Marcelo E. Kaihara, Naofumi Takagi: Bipartite Modular Multiplication p. 201
• Laszlo Hars: Fast Truncated Multiplication for Cryptographic Applications p. 211
• Martin Seysen: Using an RSA Accelerator for Modular Inversion p. 226
• B. Sunar, D. Cyganski: Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings p. 237

Side Channel II (EM)

• Catherine H. Gebotys, Simon Ho, C.C. Tiu: EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA p. 250
• Markus G. Kuhn: Security Limits for Compromising Emanations p. 265
• Huiyun Li, A. Theodore Markettos, Simon Moore: Security Evaluation Against Electromagnetic Analysis at Design Time p. 280

Side Channel III

• Marc Joye, Pascal Paillier, Berry Schoenmakers: On Second-Order Differential Power Analysis p. 293
• Eric Peeters, Fran¸cois-Xavier Standaert, Nicolas Donckers,Jean-Jacques Quisquater: Improved Higher-Order Side-Channel Attacks with FPGA Experiments p. 309

Trusted Computing

• Ulrich K¨uhn, Klaus Kursawe, Stefan Lucks, Ahmad-Reza Sadeghi,Christian St¨uble: Secure Data Management in Trusted Computing p. 324

Hardware Attacks and Countermeasures II

• Sergei Skorobogatov: Data Remanence in Flash Memory Devices p. 339
• Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede: Prototype IC with WDDL and Differential Routing – DPA Resistance Assessment p. 354

Hardware Attacks and Countermeasures III

• Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa: DPA Leakage Models for CMOS Logic Circuits p. 366
• Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet: The “Backend Duplication” Method p. 383

Efficient Hardware I

• P. Grabher, D. Page: Hardware Acceleration of the Tate Pairing in Characteristic Three p. 398
• T. Kerins, W.P. Marnane, E.M. Popovici, P.S.L.M. Barreto: Efficient Hardware for the Tate Pairing Calculation in Characteristic Three p. 412

Efficient Hardware II

• Tim Good, Mohammed Benaissa: AES on FPGA from the Fastest to the Smallest p. 427
• D. Canright: A Very Compact S-Box for AES p. 441