CHES 2000

WORCESTER, MASSACHUSETTS, USA

Çetin K. Koç, Christof Paar (Eds.): Cryptographic Hardware and Embedded Systems - CHES 2000, Second International Workshop Worcester, MA, USA, August 17-18, 2000, Proceedings. Lecture Notes in Computer Science, Vol. 1965 Springer 2000, ISBN 3-540-41455-X

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Invited Talk

• Darrel Hankerson, Julio López Hernandez, Alfred Menezes: Software Implementation of Elliptic Curve Cryptography over Binary Fields p. 1

Implementation of Elliptic Curve Cryptosystems

• Souichi Okada, Naoya Torii, Kouichi Itoh, et al.: Implementation of Elliptic Curve Cryptographic Coprocessor over GF(2m) on an FPGA p. 25
• Gerardo Orlando and Christof Paar: A High-Performance Reconfigurable Elliptic Curve Processor for GF (2m) p. 41
• Jae Wook Chung, Sang Gyoo Sim, Pil Joong Lee: Fast Implementation of Elliptic Curve Defined over GF(pm) on CalmRISC with MAC2424 Coprocessor p. 57

Power and Timing Analysis Attacks

• Adi Shamir: Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies p. 71
• Rita Mayer-Sommer: Smartly Analyzing the Simplicity and the Power of Simple Power Analysis on Smartcards p. 78
• M. Anwar Hasan: Power Analysis Attacks and Algorithmic Approaches to their Countermeasures for Koblitz Curve Cryptosystems p. 93
• Werner Schindler: A Timing Attack against RSA with the Chinese Remainder Theorem p. 109

Hardware Implementation of Block Ciphers

• Andreas Dandalis, Viktor K. Prasanna, Jose D. P. Rolim: A Comparative Study of Performance of AES Final Candidates Using FPGAs p. 125
• Cameron Patterson: A Dynamic FPGA Implementation of the Serpent Block Cipher p. 141
• Steve Trimberger, Raymond Pang, Amit Singh: A 12 Gbps DES Encryptor/Decryptor Core in an FPGA p. 156
• Herbert Leitold, Wolfgang Mayerwieser, Udo Payer, et al.: A 155 Mbps Triple-DES Network Encryptor p. 164

Hardware Architectures

• James Goodman and Anantha Chandrakasan: An Energy Efficient Reconfigurable Public-Key Cryptography Processor Architecture p. 175
• Johann Großschädl: High-Speed RSA Hardware Based on Barret's Modular Reduction Method p. 191
• Colin D. Walter: Data Integrity in Hardware for Modular Arithmetic p. 204
• Takehiko Kato, Satoru Ito, Jun Anzai, et al.: A Design for Modular Exponentiation Coprocessor in Mobile Telecommunication Terminals p. 216

Invited Talk

• David Naccache and Michael Tunstall: How to Explain Side-Channel Leakage to Your Kids p. 229

Power Analysis Attacks

• Jean-Sébastien Coron and Louis Goubin: On Boolean and Arithmetic Masking against Differential Power Analysis p. 231
• Thomas S. Messerges: Using Second-Order Power Analysis to Attack DPA Resistant Software p. 238
• Christophe Clavier, Jean-Sébastien Coron, Nora Dabbous: Differential Power Analysis in the Presence of Hardware Countermeasures p. 252

Arithmetic Architectures

• Huapeng Wu: Montgomery Multiplier and Squarer in GF(2m) p. 264
• Erkay Sava, Alexandre F. Tenca, Çetin K. Koç: A Scalable and Unified Multiplier Architecture for Finite Fields GF(p) and GF (2m) p. 277
• Gaël Hachez and Jean-Jacques Quisquater: Montgomery Exponentiation with no Final Subtractions: Improved Results p. 293

Physical Security and Cryptanalysis

• Steve H. Weingart: Physical Security Devices for Computer Subsystems: A Survey of Attacks and Defenses p. 302
• Thomas Pornin and Jacques Stern: Software-Hardware Trade-Offs: Application to A5/1 Cryptanalysis p. 318

New Schemes and Algorithms

• Jeffrey Hoffstein and Joseph H. Silverman: MiniPASS: Authentication and Digital Signatures in a Constrained Environment p. 328
• Marc Joye, Pascal Paillier, Serge Vaudenay: Efficient Generation of Prime Numbers p. 340