Senior Principal Engineer- Secure Hardware Design

Cryptography Research is experiencing tremendous demand for its tamper-resistance and DPA countermeasure technologies. This opening is for an established tamper resistance engineering expert to join our world-class DPA team, to assist vendors across a wide range of industries incorporate CRIs DPA-countermeasures and tamper-resistance technologies into their products.

Responsibilities:

• Serve as a highly visible industry expert on tamper-resistance and DPA countermeasures
• Design and implement DPA-resistant hardware blocks suitable for a variety of applications and device form factors
• Guide customers implementing DPA countermeasures and tamper resistance into their products and systems
• Consult with customers regarding their DPA-resistance certification needs
• Develop tools and training material around methodologies for DPA resistant hardware design
• Author whitepapers and technical papers related to tamper resistance, side-channel analysis and countermeasures
• Provide customer training on DPA

Requirements:

• 8+ years experience in tamper resistant hardware design and at least 5 years experience in developing DPA resistant hardware and products that use algorithms such as DES, 3DES, AES, RSA and ECC
• Deep knowledge of the statistics of DPA, sources of information leakage in hardware and engineering tradeoffs between different countermeasure choices
• Experience with getting multiple products evaluated for DPA resistance at EAL 5+
• External recognition as an expert in the area of tamper resistance, side-channel analysis and countermeasures, via publications, industry panels, contributions to standards working groups, etc.
• Very high degree of skill with Verilog (or VHDL) and digital design
• In depth understanding of front-end ASIC design flows, including design, simulation, synthesis and timing analysis
• Hardware development experience in UNIX/Linux environments, and with shell/perl scripting
• Excellent interpersonal, presentation and documentation skills
• MS/Ph.D in Electrical Engineering
• Pluses: Experience in the following areas
• Mixed mode and analog simulations for assessing DPA resistance at the design stage
• Developing tools and algorithms for performing side-channel analysis
• IP core delivery and handoff issues
• Modern SoC design methodologies and architectures

To apply for this position please click here.